Byoung-Joo Yoo

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

Byoung-Joo Yoo, Dong‐Hyuk Lim, Hyonguk Pang et al. · 2020 · 55 citations

Engineering, Low-power Dsp, Data Converter +12

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

Kihwan Seong, Donguk Park, Gyeomje Bae et al. · 2023 · 31 citations

Artificial Intelligence, Engineering, Computer Architecture +19

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

Timothy O. Dickson, Zeynep Toprak-Deniz, Martin Cochet et al. · IEEE Journal of Solid-State Circuits · 2022 · 27 citations

Engineering, Sst Drivers, Data Converter +10

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS

Abdullah Serdar Yonar, Pier Andrea Francese, Matthias Brändli et al. · 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 23 citations

Engineering, Bootstrapped Sampler, Class-ab Buffer +13

250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 $\mu$m CMOS

Sang‐Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak et al. · IEEE Journal of Solid-State Circuits · 2011 · 12 citations

Vernier Phase Shifter, Engineering, Data Converter +9