2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 23 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingDistortion AnalysisMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignCmos Analog Circuit DesignCmos Analog Integrated CircuitsHarmonic DistortionInput Common-mode RangeTotal Harmonic Distortion
A 56 GS/s 8-bit asynchronous SAR ADC fabricated in 4nm CMOS technology is demonstrated. The 16x4 interleaved ADC uses a novel bootstrapping technique and a class-AB follower in the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> rank interleaver. It achieves a broad input common-mode (CM) range; from 0.3V to 0.6V, the total harmonic distortion stays below -52dB at 4.1 GHz with -0.2dBFS amplitude at 0.8V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PPD</inf> maximum full scale. The ADC includes analog foreground calibration means for offset, gain, skew, and bandwidth. The measured ENOB is 6.5 at low frequency and stays above 5.2 up to Nyquist frequency. The bandwidth is higher than 27 GHz. The ADC uses a single 0.8V supply voltage and achieves an efficiency of 47 fJ/conv.step.