A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS

Thomas Toifl, Christian Menolfi, Michael Ruegg, +10

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignGbps Rx +12

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor

Dieter Wendel, R. Kalla, J. Warnock, +21

IEEE Journal of Solid-State Circuits

Deep Trench CapacitorsEngineeringVlsi DesignComputer ArchitectureIntegrated Circuits +20

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

Eric Fluhr, Steve Baumgartner, D. Boerstler, +27

IEEE Journal of Solid-State Circuits

EngineeringCore ThroughputEnergy EfficiencyComputer ArchitecturePower Optimization +17

5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth

Eric Fluhr, Joshua Friedrich, Daniel Dreps, +17

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsAdvanced Packaging (Semiconductors) +14

IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI

Jeffrey Stuecheli, William J. Starke, James D. Irish, +5

IBM Journal of Research and Development

Ibm Power9EngineeringComputer ArchitectureAcceleration EnablementIntegrated Circuits +15

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator

Kyu Hyun Kim, P. Coteus, Daniel Dreps, +3

Low-power Electronics4-Stage Ring OscillatorElectrical EngineeringDriven OscillatorEngineering +6

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS

R. Reutemann, Michael Ruegg, Fran Keyser, +4

IEEE Journal of Solid-State Circuits

Low-power ElectronicsOptional Cleanup PllVlsi DesignEngineeringClock Recovery +10

4.1 22nm Next-generation IBM System z microprocessor

J. Warnock, Brian Curran, John Badar, +28

Contutto

Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, +6

Hardware SecurityMemory LatencyEngineeringHardware AccelerationHigh-performance Architecture +7

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4

Christopher González, Eric Fluhr, Daniel Dreps, +11

EngineeringComputer ArchitectureProcessor FamilyHardware SystemsAccelerator Links +18