High‐performance, low‐cost, and highly reliable radiation hardened latch design

Abstract

Technology scaling results in that, soft errors, due to radiation‐induced single event double‐upset (SEDU) that affects double nodes through charge sharing, become a prominent concern in nanoscale CMOS technology. Existing hardened schemes suffer from being not fully SEDU‐immune, or perform with too large cost penalties regarding propagation delay, silicon area, and power dissipation. A novel high‐performance, low‐cost, and fully SEDU‐immune latch, referred to as HSMUF, is presented to tolerate SEDU when any arbitrary combination pair of nodes is affected by a particle striking. The latch mainly consists of a clock gating‐based triple path DICE and a multiple‐input Muller C‐element. Simulation results demonstrate the SEDU‐immunity and a 99.73% area–power–delay product saving for the HSMUF latch, compared with the SEDU fully immune DNCS‐SEUT latch.