Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction

TLDR

Single‑event effects involving multiple‑node charge collection or charge sharing are common in memory circuits, causing multiple‑cell upsets and upset of redundant logic latches. The study identifies gaps in current research and outlines potential future impacts of multiple‑node charge collection. The authors analyze how multiple‑node charge collection complicates modeling and ground‑based testing of single‑event effects. They find that multiple‑node charge collection hampers accurate soft error rate prediction, indicating that full‑circuit models remain incomplete.

Abstract

Physical mechanisms of single-event effects that result in multiple-node charge collection or charge sharing are reviewed and summarized. A historical overview of observed circuit responses is given that concentrates mainly on memory circuits. Memory devices with single-node upset mechanisms are shown to exhibit multiple cell upsets, and spatially redundant logic latches are shown to upset when charge is collected on multiple circuit nodes in the latch. Impacts on characterizing these effects in models and ground-based testing are presented. The impact of multiple-node charge collection on soft error rate prediction is also presented and shows that full circuit prediction is not yet well understood. Finally, gaps in research and potential future impacts are identified.