The impact of device scaling and power supply change on CMOS gate performance

Abstract

Based a new empirical mobility model that is solely dependent on V/sub gs/, V/sub t/, and T/sub ox/ and a corresponding saturation drain current (I/sub dsat/) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the T/sub ox/ which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V/sub dd/ (for low power applications) if V/sub t/ can be lowered.