IEEE Transactions on Semiconductor Manufacturing · 2003 · 16 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceFault-tolerant ComputingMicroelectronicsDesign For TestabilityHardware DebuggingHardware Fault ToleranceIntegrated Circuit DesignPhysical DesignVery-large-scale Integration LayoutInterconnect TestingMultiplexer Design
The complexity of integrated circuits has led to millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of <10 faults per billion, which requires test structures with huge chains of 1 million or more contacts and vias. At the same time, contacts and vias are getting smaller, and thus their resistance is increasing for every new technology node. Consequently, the resistance of such chains becomes impossible to measure. To overcome this limit without increasing the number of measurement pads, we are proposing a passive multiplexer array of via chains, which breaks up a huge contact-via chain into many individually measurable subchains. Accuracy of fail rates is increased since the fail rate can be determined based on many subchains rather than on only one huge chain. Furthermore, this test structure better supports failure analysis since it is faster to locate a faulty contact or via. No additional devices or process steps are required which allows implementation as short flows for fast process problem debugging.
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The use of a digital multiplexer to reduce process control chip pad count
D. Ward, A.J. Walton, W. Gammie et al. · 2003 · 22 citations
Engineering, Computer Engineering, Electrical Engineering +14