Integrated circuit yield management and yield analysis: development and implementation

Abstract

Integrated circuit manufacturing yields are not necessarily a function of chip area. Accurate yield analysis shows how the yield depends on circuit design and layout. By determining the probabilities of failure and critical areas for different defect types, it is possible to control and manage the yield of integrated circuits. This includes the manufacture of DRAM's, SRAM's, CMOS logic, ASIC's, and CMOS and biCMOS microprocessors. Examples explain the method of meeting yield objectives by setting targets for yield components. In addition, the yield management approach allows for a systematic allocation of resources. Required defect-density learning determines the contamination levels for clean rooms and process equipment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>