VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits

TLDR

The defect statistical model underlying VLASIC is derived from real fabrication line data and is novel in the literature. This paper introduces VLASIC, a yield simulator for VLSI layouts. VLASIC is a Monte Carlo simulator that places random catastrophic point defects on a chip layout using table‑based defect models, then identifies resulting circuit faults, and its models are easily extendable to new processes or defect types. The simulator’s fault data enable yield prediction, design rule optimization, test vector generation, and redundancy evaluation, as illustrated by a redundancy analysis system example.

Abstract

This paper describes the yield simulator VLASIC (VLSI Layout Simulation for Integrated Circuits). VLASIC is a Monte Carlo simulator that uses defect models and statistics to place random catastrophic point defects on a chip layout and determine what circuit faults, if any, have occurred. The defect models are described in tables, and so are readily extended to new processes or defect types. The defect statistical model is based on actual fabrication line data, and has not appeared before in the literature. The circuit fault information generated by VLASIC can be used to predict yield, optimize design rules, generate test vectors, evaluate redundancy, etc. A redundancy analysis system which uses these data is described, and an example of its use given.