2002 · 26 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceMicroelectronicsSemiconductor DevicesBuilt-in Self-testComputer-based TestingDesign For TestabilityDevice CharacterizationBoundary ScanBoundary Scan ArchitectureBoundary Scan TestingDigital Circuit Self-testingEmbedded TestLogic Built-in Self-testLow-cost Built-in Self-testPins
Testing for IC pin leakage current is important because it detects many subtle I/O circuitry faults. A technique is introduced in which the leakage current of pins is tested (or measured) during wafer probing using existing 1149.1 boundary scan access only - the tested pins are not contacted The technique requires every tested pad to have a tristate driver and receiver ("I/O wrap"), and relies on knowing approximately each pad's capacitance and each receiver's switching point voltage. Experimental results for a 500 signal-pin IC, that also contained an embedded test for the logic, show that the test program is simplified and runs on a very low cost tester in a reduced test time, while overall yield is maintained or improved.
5
Early capture for boundary scan timing measurements
K. Lofstrom · 2002 · 62 citations
Low-cost testing of high-density logic components
R.W. Bassett, B.J. Butkus, S.R. Dingle et al. · IEEE Design & Test of Computers · 1990 · 41 citations
Engineering, Computer Engineering, Electrical Engineering +15
Delay test of chip I/Os using LSSD boundary scan
P.S. Gillis, Frank Woytowich, K. McCauley et al. · 2002 · 40 citations
Engineering, Computer Engineering, Electrical Engineering +15