Effect of impact pulse parameters on consistency of board level drop test and dynamic responses

Abstract

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. JEDEC standard for board level drop test of handheld electronic products addresses requirements from test board design, material, construction and assembly of test board, component location, tester setup, and reporting format in details. However, the effects of peak acceleration, duration, and shape of impact pulse are not emphasized there, which should be key variables that affect the solder joint reliability during drop impact. In this paper, effect of impact pulse is investigated by both theoretical analysis and numerical modeling. The input acceleration (input-G) method established is a convenient tool to verify the conclusions made from theoretical analysis. The results show that not only the peak acceleration and pulse duration, but also the pulse shape and area under impact pulse significantly affect the solder joint performance during drop test. The variations of peak acceleration pulse duration, and pulse shape usually induce significant scattering of drop test results due to different testers, or operators although the impact pulses are all within JEDEC test specification. Therefore, the specification of impact pulse should be tightened. For this sake, electronic product manufacturers should have some strategy to minimize such effects for component qualification or selection. The stress levels under different test conditions are also examined. Numerical modeling makes it possible to convert the drop test result from one test condition to another test conditions without performing additional drop tests, and thus saving time and cost. Acceleration factors for different test conditions can be obtained based on good correlation of drop impact life between experiment and modeling.