2002 · 63 citations · 17 references
EngineeringComputer EngineeringComputer ScienceExperimental PerformanceTest ConstructionTest DevelopmentComputer-based TestingDesign For TestabilityArea Overhead AnalysisFault CoverageFault Coverage AnalysisTest Compression
This paper presents a new test resource partitioning scheme that is a hybrid approach between external testing and BIST. It reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. The proposed approach is based on weighted pseudo-random testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. No test points or any modifications are made to the function logic. The proposed scheme requires adding only a small amount of additional hardware to the STUMPS architecture. Experimental results comparing the proposed approach with other approaches are presented.
17
Logic BIST for large industrial designs: real issues and case studies
G. Hetherington, T. Fryars, N. Tamarapalli et al. · 2003 · 284 citations
Engineering, Computer Engineering, Electrical Engineering +16
Self-Testing of Multichip Logic Modules.
Paul H. Bardell, W.H. McAnney · International Test Conference · 1982 · 270 citations