Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide

Abstract

We have investigated the electrical characteristics of gate oxide films deposited by plasma enhanced chemical vapor deposition (PECVD) with respect to gate oxide integrity (GOI) and its reliability. In the investigation, post-annealed gate oxide was compared with as-deposited oxide. It was shown that the characteristics of GOI strongly depended on the charge trapping characteristics and deep level interface states generation under FN stress, which was remarkably improved by post-annealing after gate oxide deposition. Improved FN stress and hot carrier stress reliability of CMOS devices implemented on the glass substrate are also discussed.