SRAM leakage in CMOS, FinFET and CNTFET technologies

Abstract

An in-depth study of the static power consumption in 6T and 8T SRAM cell designs based on 32nm CMOS, FinFET and CNTFET technologies is presented. In addition to the inverter leakage currents, memory cells that are not active when write or read operations occur draw current from/to the bus drivers increasing the total standby power consumption. The FinFET schemes yield substantially lower write (1023.5 pA) and read (522.5 pA) leakage currents in 8T cells, which are 10.4% and 4.4% of the amount in CMOS 8T cells. A CNTFET 6T cell consumes 1.9% and 2.8% of the leakage current drawn by a CMOS 6T cell for write and read.