IEEE Electron Device Letters · 2007 · 83 citations · 8 references
EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsVlsi DesignCmos Circuit DesignIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsCutoff FrequencyDesign MethodologyDevice OptimizationFin Field-effect TransistorsLow-voltage Cmos DesignSource-drain Engineering
In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T </sub> ) of 25-nm gate-length FinFETs operated at low drain-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> (~45 dB) and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs
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Quantum-mechanical effects in trigate SOI MOSFETs
J.-P. Colinge, J. Alderman, Weize Xiong et al. · IEEE Transactions on Electron Devices · 2006 · 132 citations