Chip package interaction (CPI): Thermo mechanical challenges in 3D technologies

Abstract

The residual stresses generated during different processing steps and during thermal cycling of 3D stack packages, mimicking its service life, are quantified by Finite Element Modeling (FEM) together with measurements of dedicated FET arrays used as CPI sensors. Thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The test vehicle used in this work is an imec's proprietary logic CMOS IC on top of which a commercial DRAM is stacked. Different test structures contained in the chip, allow monitoring thermo-mechanical stresses and electrical characteristics of TSV's and micro-bumps. It is shown that FET current shifts can be used to measure the stress in the surface of the chip. The use of standard FEM approach is insufficient to simulate the CPI due to the large dimensional difference between the packaging and interconnects structures. Due to size and speed limitations of commercial computers, a 3D thermo mechanical model of a 3D package cannot contain all the details from the package and at the same time simulate the small structures such as metal and dielectric layers in the BEOL. For this reason, multi-scale simulations are the best choice for identifying the critical regions of the package where high stresses and/or delamination failures are expected to occur. We have shown the methodology to follow to study the CPI.