IEEE Electron Device Letters · 1999 · 70 citations · 7 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsComplementary Metal-oxide-semiconductor TechnologyCurrent-voltage CharacteristicsIntegrated Circuit DesignLeakage Power ReductionMetal-oxide-semiconductor Field-effect TransistorsLatch TechniqueLeakageRing StructureSilicon-on-insulator TechnologyTunnel JunctionsTunneling CurrentTunneling DiodesTunneling In Semiconductors
This letter reports excellent negative differential conductance (NDC) characteristics at room temperature in a three-terminal silicon surface junction tunneling (Si SJT) device, with the peak-to-valley current ratio of more than two. The tunneling device was fabricated on a SIMOX wafer to achieve an extremely small bulk leakage current together with a sharp drain impurity profile. In addition, a ring-shaped gate structure was employed to eliminate the effect of the field oxide corner, resulting in the significant reduction of an excess tunneling current at the tunneling junction. As a simple circuit demonstration, gate-controlled latch characteristics are also shown, which cannot be easily achieved by a two-terminal tunneling device.
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L. Esaki · IEEE Transactions on Electron Devices · 1976 · 102 citations
Natural Sciences, Electrical Engineering, Materials Science +8
A CV technique for measuring thin SOI film thickness
J. Chen, R. Solomon, T.Y. Chan et al. · IEEE Electron Device Letters · 1991 · 69 citations