An nMOS VLSI process for fabrication of a 32-bit CPU chip

Abstract

An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency. The technology utilizes 1.5-/spl mu/m lines and 1.0-/spl mu/m spaces on all critical levels, and provides tungsten dual layer metallization. The device and interconnect structure for this 8-mask process is outlined as a sequence through the process flow. Linewidth and alignment statistics are given for the optical reduction-projection step-and-repeat lithography used in this technology.