Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines

Abstract

Transistor aging effects are more and more a major concern for device scientists, trying to integrate reliable circuits in unreliable ultra-scaled CMOS processes. Circuit design margins, to guarantee reliable analog circuit operation, are no longer sufficient and result in huge circuit overdesign. This paper discusses i) the most important transistor aging effects, ii) how designers can evaluate their impact on circuits and iii) design guidelines on which circuits are sensitive to transistor aging. Circuit parameters such as amplifier gain, bandwidth and slewrate are shown to be immune to transistor aging, while variation-sensitive parameters such as offset, the output current of a current mirror and the on-resistance of a MOS-resistor are very prone to transistor aging. Furthermore, to help a designer estimate the impact of aging on his/her circuit and to find a good reliability-performance tradeoff, a first-order transistor aging model is provided.