Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes

Abstract

A statistical metrology framework is used to identify systematic and random sources of interconnect structure (ILD thickness) variation. Electrical and physical measurements, TCAD simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve ILD thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative CMP process we find that die-level neighborhood interactions are comparable to die-level feature-dependent effects, and within each die, die-level variation is greater than wafer-level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.