Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

Abstract

A high-voltage lateral double diffused metal-oxide-semiconductor transistor on partial silicon on insulator (PSOI) with a buried low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric (LK PSOI) is proposed. The low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> value enhances the electric field strength in the dielectric ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EI</i> ). The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EI</i> and BV of LK PSOI with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">kI</i> = 2 are enhanced by 74% and 19%, respectively.