Imprint lithography for integrated circuit fabrication

TLDR

The escalating cost of next‑generation lithography tools, driven by complex sources and optics, could exceed $50 M, making them prohibitive for many companies, and early research in the 1990s explored imprinting techniques that, while effective across wafers, struggled with precise overlay and are now known as step‑and‑flash imprint lithography. This article traces the development of nanoimprint lithography and seeks to identify the challenges that must be overcome for its application to high‑density silicon integrated circuitry. The technique uses a quartz template to photocure low‑viscosity UV monomers, enabling low‑pressure.

Abstract

The escalating cost for next generation lithography (NGL) tools is driven in part by the need for complex sources and optics. The cost for a single NGL tool could exceed $50M in the next few years, a prohibitive number for many companies. As a result, several researchers are looking at low cost alternative methods for printing sub-100 nm features. In the mid-1990’s, several research groups started investigating different methods for imprinting small features. Many of these methods, although very effective at printing small features across an entire wafer, are limited in their ability to do precise overlay. In 1999, Colburn et al. [Proc. SPIE 379 (1999)] discovered that imprinting could be done at low pressures and at room temperatures by using low viscosity UV curable monomers. The technology is typically referred to as step and flash imprint lithography. The use of a quartz template enabled the photocuring process to occur and also opened up the potential for optical alignment of the wafer and template. This article traces the development of nanoimprint lithography and addresses the issues that must be solved if this type of technology is to be applied to high-density silicon integrated circuitry.