Proceedings - ACM IEEE Design Automation Conference · 2002 · 58 citations · 27 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ModelingIntegrated Circuit DesignIntegrated Circuit DevicesPhysical DesignCmos Fabrication ProcessesCmos Logic CircuitsCmos Logic DesignCmos ScalingFabrication ProcessesMemory Circuit DesignSingle-electron Transistors
The paper reviews CMOS evolution, its limitations, and the working principles, performance, and fabrication of single‑electron transistors, while outlining future efforts needed for CMOS‑SET hybrid memory and logic circuits. The authors compare two novel SET architectures, C‑SET and R‑SET, designed for logic applications, and discuss their characteristics within the context of CMOS evolution and SET fabrication. SETs offer unrivalled integration and low power complementary to sub‑20 nm CMOS, and combining CMOS with SETs in hybrid ICs yields attractive new functionality, performance, and improved integrability for ULSI.
In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics and functionality of SETs, like unrivalled integration and low power, which are complementary to the sub-20 nm CMOS, are demonstrated. Characteristics of two novel SET architectures, namely, C-SET and R-SET, aimed at logic applications are compared. Finally, it is shown that combination of CMOS and SET in hybrid ICs appears to be attractive in terms of new functionality and performance, together with better integrability for ULSI, especially because of their complementary characteristics. It is envisioned that efforts in terms of compatible fabrication processes, packaging, modeling, electrical characterization, co-design and co-simulation will be needed in the near future to achieve substantial advances in both memory and logic circuit applications based on CMOS-SET hybrid circuits.
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A silicon nanocrystals based memory
Sandip Tiwari, Farhan Rana, Hussein Hanafi et al. · Applied Physics Letters · 1996 · 1.6K citations
Single-electron devices and their applications
K. K. Likharev · Proceedings of the IEEE · 1999 · 1.5K citations
CMOS scaling into the nanometer regime
Yuan Taur, D. A. Buchanan, Wei Chen et al. · Proceedings of the IEEE · 1997 · 889 citations
Engineering, Computer Engineering, Electrical Engineering +17