2003 · 38 citations · 20 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault-tolerant ComputingSystem-on-chip DesignBuilt-in Self-testDesign For TestabilityEmbedded Memory BlocksHardware Fault ToleranceMemory Subsystem DesignProcessor Core DesignArea Overhead AnalysisAt-speed TestingBuilt-in Self-repairMemory Built-in Self-repairMemory Built-in Self-testRedundancy AllocationRedundancy AnalysisSelf-repairing Hardware
We propose an embedded processor-based built-in self-repair (BISR) design for embedded memories. In the proposed design we reuse the embedded processor that can be found on almost every system-on-chip (SOC) product, in addition to many distinct features. By reusing the embedded processor, the controller and redundancy analysis circuit of a typical BISR design can be removed. Also, the test algorithm and redundancy analysis/allocation algorithm are easily programmable, greatly increasing the design flexibility. We also have developed a memory wrapper that allows at-speed testing of the memory cores. The area overhead of the proposed BISR scheme is low, since only the memory wrapper needs to be realized explicitly. Our experiments show that the BISR area overhead for a typical 8 K/spl times/32 SRAM is lower than 1%.
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Built in self repair for embedded high density SRAM
Ilyoung Kim, Y. Zorian, G. Komoriya et al. · 2002 · 196 citations
Engineering, Computer Engineering, Electrical Engineering +17
Built-in redundancy analysis for memory yield improvement
Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li et al. · IEEE Transactions on Reliability · 2003 · 192 citations
Engineering, Computer Engineering, Electrical Engineering +17
A built-in self-repair analyzer (CRESTA) for embedded DRAMs
Takeshi Kawagoe, J. Ohtani, M. Niiro et al. · 2002 · 170 citations
Engineering, Computer Engineering, Electrical Engineering +16
A programmable BIST core for embedded DRAM
Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu et al. · IEEE Design & Test of Computers · 1999 · 125 citations