Memory Built-In Self-Test is a design-for-testability technique that integrates self-contained circuitry within a semiconductor device to autonomously generate test patterns, apply them to embedded memory arrays, and evaluate responses for fault detection without external test equipment.
256
Publications
8.5K
Citations
720
Authors
196
Institutions
Publications per year
2017–2026
27
Variants
Mbist
Publications
256
Built-in redundancy analysis for memory yield improvement
Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li et al. · IEEE Transactions on Reliability · 2003 · 192 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 256
Authors
720
- CW
17
h-index
- YZ
13
h-index
- AV
11
h-index
- SH
10
h-index
- SS
9
h-index
1–5 of 720
Institutions
196
National Tsing Hua University
Hsinchu, Taiwan
17 h-index
85 publications
3.2K citations
Delft University of Technology
Delft, The Netherlands
15 h-index
45 publications
1.5K citations
IBM (United States)
Armonk, United States
12 h-index
73 publications
1.7K citations
Intel (United States)
Santa Clara, United States
11 h-index
28 publications
846 citations
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
Montpellier, France
10 h-index
32 publications
878 citations
Centre National de la Recherche Scientifique
Paris, France
9 h-index
31 publications
746 citations
Université de Montpellier
Montpellier, France
8 h-index
29 publications
768 citations
Philips (Netherlands)
Amsterdam, The Netherlands
8 h-index
14 publications
485 citations
1–8 of 196
Venues
- IEEE Journal of Solid-State Circuits
16 publications · 470 citations
14
h-index
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
11 publications · 257 citations
11
h-index
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
10 publications · 308 citations
10
h-index
- IEEE Design & Test of Computers
10 publications · 754 citations
10
h-index
- IEEE Transactions on Computers
8 publications · 662 citations
8
h-index
1–5