Benoit Nadeau-Dostie

Author

McGill University

Also Known As

B. Nadeau-Dostie, Benoit Nadeau-Dostie, Benoit NadeauDostie, Nadeau-Dostie Benoit, Nadeau-Dostie, Benoit

Publications

927

Citations

H-Index

Concepts

All Affiliations

McGill University Nortel (Canada)Bell (Canada)Mentor Technologies The University of Texas at Austin

About

Benoit Nadeau-Dostie is an author at McGill University specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	15	20	790
2	Computer Engineering	15	19	773
3	Electrical Engineering	12	12	333
4	Computer Science	6	6	395
5	Education	2	2	80

Benoit Nadeau-Dostie

Publications

801

Citations

H-Index

Page 1

	Year	Citations
A new procedure for weighted random built-in self-test Fidel Muradali, V.K. Agarwal, Benoit Nadeau-Dostie EngineeringMem TestingComputer ArchitectureWeighted StreamIntegrated Circuits	2002	161
Serial interfacing for embedded-memory testing Benoit Nadeau-Dostie, A.L. Silburt, V.K. Agarwal IEEE Design & Test of Computers EngineeringMem TestingComputer ArchitectureEmbedded SystemsHardware Systems	1990	148
BIST of PCB interconnects using boundary-scan architecture A.S.M. Hassan, V.K. Agarwal, Benoit Nadeau-Dostie, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringMem TestingComputer ArchitectureIntegrated CircuitsHardware Systems	1992	67
ScanBist: a multifrequency scan-based BIST method Benoit Nadeau-Dostie, D. Burek, A.S.M. Hassan IEEE Design & Test of Computers EngineeringComputer ArchitectureEducationHardware SystemsArray Computing	1994	52
An embedded technique for at-speed interconnect testing Benoit Nadeau-Dostie, J-F Cote, H. Hulvershorn, Hardware SecurityElectrical EngineeringEngineeringBoundary Scan StandardHardware-in-the-loop Simulation	2003	41
Test generator with preselected toggling for low power built-in self-test J. Rajski, Jerzy Tyszer, Grzegorz Mrugalski, EngineeringPseudo-random SequenceComputer ArchitectureBinary SequencesTest Generator	2012	36
Low-Power Programmable PRPG With Test Compression Capabilities Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, IEEE Transactions on Very Large Scale Integration (VLSI) Systems EngineeringTest Power EnvelopeHardware AlgorithmComputer ArchitectureBinary Sequences	2014	36
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie IEEE Transactions on Computers EngineeringTest Point InsertionMem TestingComputer ArchitectureHardware Systems	2011	32
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-François Côté EngineeringVlsi DesignMeasurementComputer ArchitectureEducation	2008	28
Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost S.K. Sunter, Benoit Nadeau-Dostie Hardware SecuritySystem On ChipElectrical EngineeringEngineeringVlsi Design	2003	28

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