Latch-up on CMOS/EPI devices

Abstract

A dedicated latch-up test system has been developed and was used on two beam lines, the GANIL cyclotron and the IPN Tandem Van de Graaff located in Caen and Orsay (France). The main characteristics of these facilities are presented. Several VLSI circuits were irradiated, and the latchup phenomenon was detected on eight CMOS/EPI devices, revealing various ranges of sensitivity. Recording of the value and rising edge of latchup current was also performed. The problem of whether or not latchup-sensitive circuits should be used for space projects and the need for studies of component design hardening, system design hardening, and latchup rate prediction are addressed. Data are presented on several CMOS/EPI devices demonstrating that an epitaxial layer cannot efficiently achieve latchup immunity for some of the latest technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>