IEEE Journal of Solid-State Circuits · 1988 · 32 citations · 13 references
Electrical EngineeringMemory ArchitectureEngineering63-Ff Storage CapacitanceEmerging Memory TechnologySmall ChipComputer EngineeringComputer ArchitectureMemory DevicesSemiconductor MemoryIntegrated Circuits16-Mb Dynamic Ram16-Mbit DramMicroelectronicsMemory ReliabilityMulti-channel Memory Architecture
A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A trench transistor cross-point DRAM cell
W.F. Richardson, D.M. Bordelon, G. Pollack et al. · 1985 · 47 citations
Circuit technologies for 16Mb DRAMs
T. Mano, Takeshi Matsumura, J. Yamada et al. · 1987 · 37 citations
Hardware Security, Non-volatile Memory, Electrical Engineering +11
A 4-Mbit DRAM with trench-transistor cell
A.H. Shah, C. Wang, R.H. Womack et al. · IEEE Journal of Solid-State Circuits · 1986 · 31 citations
A 16mb Dram with an Open Bit-Line Architecture
Inoue, Kotani, Yamada et al. · 1988 · 31 citations
Open Bit-line Architecture, Engineering, Computer Engineering +4