IEEE Electron Device Letters · 1997 · 102 citations · 8 references
Semiconductor TechnologyElectrical EngineeringEngineeringHigh Voltage EngineeringPower DeviceSic UmosfetsElectronic EngineeringBias Temperature InstabilityApplied PhysicsPower Semiconductor DevicePlanar 6H-sic AccufetPoor Channel ConductancePower ElectronicsPower SemiconductorsMicroelectronicsChannel RegionSemiconductor Device
A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P/sup +/ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 m/spl Omega/.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10/sup 16/ cm/sup -3/, 10 μm), which is capable of supporting 1500 V.
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SiC devices: physics and numerical simulation
M. Ruff, H. Mitlehner, R. Helbig · IEEE Transactions on Electron Devices · 1994 · 498 citations