2003 · 15 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsDigital Integrated Circuit DesignInterconnect ArchitectureInterconnect DesignLow-power Cache DesignLow-power Digital Circuit DesignProcessor Core DesignClock Network ArchitectureClock Network Power ReductionClock Skew OptimizationLow-power Instruction Cache DesignOn-chip Clock Power OptimizationParallel Computing ArchitecturesVerification Methodology
This 130nm Itanium® 2 processor implements the Explicitly Parallel Instruction Computing (EPIC) architecture and features an on-die 6MB, 24-way set associative L3 cache. The 374mm2 die contains 410M transistors and is implemented in a dual-Vt process with 6 layers copper interconnect and FSG dielectric. The processor runs at 1.5GHz at 1.3V and dissipates a maximum of 130W. This paper reviews circuit design and package details, power delivery, RAS, DFT and DFM features, as well as an overview of the design and verification methodology. The fuse-based clock de-skew circuit achieves 24ps skew across the entire die, while the scan-based skew control further reduces it to 7ps. The 128-bit front-side bus supports up to 4 processors on a single bus with a bandwidth of up to 6.4GB/s.
4
The first IA-64 microprocessor
Stefan Rusu, G. Singer · IEEE Journal of Solid-State Circuits · 2000 · 66 citations
Engineering, Computer Engineering, Electrical Engineering +17