Clock Skew Optimization
Clock Skew Optimization is a method in the domain of clock distribution networks and timing closure that minimizes timing mismatches between clock signals arriving at different sequential elements by strategically adjusting clock path delays through buffer insertion, wire sizing, or routing modifications.
301
Publications
10.9K
Citations
591
Authors
166
Institutions
Publications per year
2017–2026
8
301
J.P. Fishburn · IEEE Transactions on Computers · 1990 · 520 citations
Engineering, Computer Engineering, Electrical Engineering +17
Clock routing for high-performance ICs
M.A.B. Jackson, Arvind Srinivasan, E.S. Kuh · 1990 · 228 citations
Engineering, Computer Engineering, Electrical Engineering +16
1–5 of 301
591
13
h-index
12
h-index
11
h-index
11
h-index
11
h-index
1–5 of 591
166
Intel (United States)
Santa Clara, United States
19 h-index
56 publications
4.4K citations
The University of Texas at Austin
Austin, United States
16 h-index
54 publications
2.1K citations
Texas A&M University
College Station, United States
14 h-index
50 publications
1.6K citations
University of California, Los Angeles
Los Angeles, United States
12 h-index
25 publications
2.9K citations
Iowa State University
Ames, United States
10 h-index
18 publications
849 citations

University of Rochester
Rochester, United States
10 h-index
13 publications
570 citations
University of California San Diego
San Diego, United States
10 h-index
27 publications
638 citations
Georgia Institute of Technology
Atlanta, United States
10 h-index
25 publications
924 citations
1–8 of 166
30 publications · 1K citations
21
h-index
13 publications · 461 citations
11
h-index
8 publications · 738 citations
8
h-index
Conference · 7 publications · 167 citations
7
h-index
ICCAD · 6 publications · 112 citations
6
h-index
1–5