Clock routing for high-performance ICs

Abstract

In this paper we focus on routing techniques for opti-mizing clock signals in small-cell (e.g., standard-cell, sea-of gate, etc...) ASICs. In previously reported work, the routin P of the clock net has been ordinary g obal routing techniques base a” erformed using on a minimum or minimal Steiner tree that have little under-of clock routing problems. We F resent a novel to clock routing that all but e rminates clock yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum fea-ture sizes, and pin distributions on both randomly cre-ated and standard industrial benchmarks. For certain classes of pin distributions we have proven theoretically and observed exnerimentallv a decrease in skew with an increase in net Bize. In practice, we have observed a two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree.