IEEE Journal of Solid-State Circuits · 2000 · 66 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsParallel ComputingInstruction Set ArchitectureMicroarchitecture DesignMulticore Processor DesignParallel ArchitecturesProcessor Core DesignProcessor MicroarchitectureBinary CompatibilityHigh PerformanceInstruction Set MicroarchitectureMany-core ArchitectureMetal Sacrificial LayersMicroarchitecture PerformanceMulticore Processor ArchitectureParallel Instruction Fetch
The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-/spl mu/m CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache.
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100 nm gate length high performance/low power CMOS transistor structure
T. Ghani, S. Ahmed, P. Aminzadeh et al. · 2003 · 60 citations