Parallel Instruction Fetch

Parallel Instruction Fetch is a processor-level mechanism in superscalar architectures that enables the simultaneous retrieval of multiple instructions from different program memory locations within a single clock cycle, thereby increasing instruction-level parallelism by overlapping the fetch stages of independent instructions.

35

Publications

3.1K

Citations

75

Authors

25

Institutions

Publications per year

2017–2026

0

Authors

75

  1. GS
    Gurindar S. Sohi

    University of Wisconsin–Madison, United States

    6 publications · 1.5K citations

    6

    h-index

  2. RH
    R. Horst

    Tandem Diabetes Care (United States), United States

    3 publications · 79 citations

    3

    h-index

  3. TN
    T. N. Vijaykumar

    Purdue University West Lafayette, United States

    3 publications · 1.1K citations

    3

    h-index

  4. RL
    Richard L. Harris

    Baylor College of Medicine, United States

    3 publications · 79 citations

    3

    h-index

  5. RL
    Robert L. Jardine

    Tandem Diabetes Care (United States), United States

    3 publications · 79 citations

    3

    h-index

1–5 of 75

Venues

  1. ACM SIGARCH Computer Architecture News

    3 publications · 193 citations

    3

    h-index

  2. IEEE Journal of Solid-State Circuits

    3 publications · 287 citations

    3

    h-index

  3. IEEE Micro

    2 publications · 145 citations

    2

    h-index

  4. IEEE Transactions on Computers

    2 publications · 270 citations

    2

    h-index

  5. Proceedings of the International Conference on Parallel Processing

    Conference · 1 publications · 42 citations

    1

    h-index

1–5