Parallel Instruction Fetch
Parallel Instruction Fetch is a processor-level mechanism in superscalar architectures that enables the simultaneous retrieval of multiple instructions from different program memory locations within a single clock cycle, thereby increasing instruction-level parallelism by overlapping the fetch stages of independent instructions.
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3.1K
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2017–2026
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Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar · 1995 · 978 citations
The microarchitecture of superscalar processors
James E. Smith, Gurindar S. Sohi · Proceedings of the IEEE · 1995 · 309 citations · Full text
Balancing thoughput and fairness in SMT processors
Kun Luo, Jayanth Gummaraju, M. Franklin · 2005 · 247 citations
The implementation of the Itanium 2 microprocessor
Samuel Naffziger, Glenn Colon-Bonet, Tim Fischer et al. · IEEE Journal of Solid-State Circuits · 2002 · 192 citations
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University of Wisconsin–Madison
Madison, United States
6 h-index
16 publications
4.1K citations
Intel (United States)
Santa Clara, United States
5 h-index
14 publications
969 citations
Carnegie Mellon University
Pittsburgh, United States
2 h-index
4 publications
50 citations
Tandem Diabetes Care (United States)
San Diego, United States
2 h-index
6 publications
180 citations

University of Massachusetts Amherst
Amherst Center, United States
2 h-index
4 publications
540 citations

Cornell University
Ithaca, United States
2 h-index
5 publications
466 citations
University of Massachusetts Boston
Boston, United States
1 h-index
1 publications
198 citations

Christian-Albrechts-Universität zu Kiel
Kiel, Germany
1 h-index
5 publications
185 citations
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3 publications · 193 citations
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3 publications · 287 citations
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2 publications · 145 citations
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2 publications · 270 citations
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Conference · 1 publications · 42 citations
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