On-chip Clock Power Optimization

On-Chip Clock Power Optimization is a methodology within low-power integrated circuit design that specifically addresses the minimization of dynamic and static power consumption associated with the clock distribution network in digital microelectronics by optimizing clock signal propagation, skew, and gating at the circuit and architecture levels.

Publications

921

Citations

128

Authors

Institutions

Publications per year

2017–2026

Parents

Power Optimization

Publications

A 160 MHz 32 b 0.5 W CMOS RISC microprocessor

J. Montanaro, Richard T. Witek, K. Anne et al. · 2002 · 118 citations

Engineering, Computer Engineering, Electrical Engineering +16

Design of Sequential Elements for Low Power Clocking System

Peiyi Zhao, Jason McNeely, Weidong Kuang et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2010 · 84 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining

Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti et al. · 2011 · 65 citations

Engineering, Computer Engineering, Computer Science +17

Pipeline muffling and a priori current ramping

Michael D. Powell, T. N. Vijaykumar · 2003 · 58 citations

Engineering, Computer Engineering, Electrical Engineering +17

An integrated 9-channel time digitizer with 30 ps resolution

A. Mantyniemi, Timo Rahkonen, Juha Kostamovaara · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 57 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 31

Authors

128

XH
Xuchu Hu
Sun Yat-sen University, China
2 publications · 45 citations
2
h-index
CZ
Cheng Zhuo
Zhejiang University, China
2 publications · 23 citations
2
h-index
VM
Varun Mittapalli
Missouri University of Science and Technology, United States
2 publications · 23 citations
2
h-index
MR
Matthew R. Guthaus
University of California, Santa Cruz, United States
2 publications · 45 citations
2
h-index
UR
Umamaheswara Rao Tida
Missouri University of Science and Technology, United States
2 publications · 23 citations
2
h-index

1–5 of 128

Institutions

1–8 of 37

Venues

IEEE Journal of Solid-State Circuits
2 publications · 64 citations
2
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2 publications · 100 citations
2
h-index
IEEE Transactions on Circuits & Systems II Express Briefs
2 publications · 31 citations
2
h-index
IEEE Transactions on Circuits and Systems I Regular Papers
2 publications · 38 citations
2
h-index
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
Conference · 1 publications · 57 citations
1
h-index

1–5