2011 · 65 citations · 5 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMicroelectronicsClock ManagementHardware AccelerationLow-power Digital Circuit DesignPower ManagementProcessor Core DesignTiming AnalysisClock Network Power ReductionHardware PipeliningLatch DesignLow-power Latch DesignOn-chip Clock Power OptimizationPipeline DesignProcess Variation AnalysisTiming Overhead Analysis
In this paper, the authors also show how clocking overhead can be reduced through circuit techniques to facilitate super pipelining while process variation is addressed through the use of latch-based design. Additionally, architecture modifications are proposed to improve energy efficiency and throughput. Measurements show that the FFT core consumes 17.7nJ per 1024-pt complex FFT while operating at 30MHz at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> =0.27V, demonstrating an improvement over the FFT energy efficiency.
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