Clock Network Power Reduction

Clock Network Power Reduction is a methodological approach within low-power digital circuit design that specifically targets the minimization of dynamic and static power dissipation in the clock distribution network through optimized circuit topology, clock gating strategies, and voltage-scalable design techniques.

246

Publications

8.2K

Citations

728

Authors

185

Institutions

Publications per year

2017–2026

Parents

Low-power Digital Circuit Design

Publications

246

Power considerations in the design of the Alpha 21264 microprocessor

M.K. Gowan, Larry Biro, Daniel B. Jackson · 1998 · 370 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

John W. Poulton, R. Palmer, Andrew M. Fuller et al. · IEEE Journal of Solid-State Circuits · 2007 · 240 citations

Engineering, Computer Engineering, Electrical Engineering +17

The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor

Samuel Naffziger, Blaine Stackhouse, T. Grutkowski et al. · IEEE Journal of Solid-State Circuits · 2005 · 204 citations

Engineering, Computer Engineering, Computer Science +17

USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA

Caio Araujo T. Campos, Abner Luis Panho Marciano, Omar P. Vilela Neto et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2015 · 181 citations

Engineering, Computer Engineering, Electrical Engineering +17

Adaptive supply serial links with sub-1-V operation and per-pin clock recovery

J. Kim, Mark Horowitz · IEEE Journal of Solid-State Circuits · 2002 · 178 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 246

Authors

728

JH
Jiang Hu
Texas A&M University, United States
9 publications · 217 citations
9
h-index
MR
Matthew R. Guthaus
University of California, Santa Cruz, United States
8 publications · 171 citations
8
h-index
PR
P.J. Restle
IBM (United States), United States
6 publications · 331 citations
6
h-index
DZ
David Z. Pan
The University of Texas at Austin, United States
5 publications · 168 citations
5
h-index
DJ
Deog‐Kyoon Jeong
Seoul National University, South Korea
4 publications · 79 citations
4
h-index

1–5 of 728

Institutions

185

1–8 of 185

Venues

IEEE Journal of Solid-State Circuits
24 publications · 1.6K citations
20
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
18 publications · 648 citations
15
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
10 publications · 585 citations
10
h-index
IEEE Transactions on Circuits & Systems II Express Briefs
4 publications · 91 citations
4
h-index
IEEE Transactions on Circuits and Systems I Regular Papers
4 publications · 73 citations
4
h-index

1–5