Concepedia

Hardware Pipelining

Hardware Pipelining is a register-transfer level design technique that belongs to the class of concurrency-exploiting architectural optimizations, distinguished by its method of decomposing a computational process into sequential stages that operate simultaneously on distinct data to increase throughput.

502

Publications

19.9K

Citations

1.2K

Authors

360

Institutions

Publications per year

2017–2026

41

Parents

Publications

502

Sehwa: a software package for synthesis of pipelines from behavioral specifications

N. Park, Alice C. Parker · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988 · 395 citations

, , +15

The design of an asynchronous MIPS R3000 microprocessor

Alain J. Martin, Andrew Lines, Rajit Manohar et al. · 2002 · 325 citations

, , +15

REAL: a program for REgister ALlocation

Fadi Kurdahi, Alice C. Parker · 1987 · 312 citations

, , +12

Available instruction-level parallelism for superscalar and superpipelined machines

Norman P. Jouppi, D. W. Wall · ACM SIGARCH Computer Architecture News · 1989 · 277 citations · Full text

, , +17

Reducing the cost of branches

Scott McFarling, J. Hennesey · ACM SIGARCH Computer Architecture News · 1986 · 263 citations

, , +12

1–5 of 502

Authors

1.2K

  1. KK
    Keshab K. Parhi

    University of Minnesota, United States

    14 publications · 556 citations

    14

    h-index

  2. MS
    Montek Singh

    University of North Carolina at Chapel Hill, United States

    12 publications · 543 citations

    11

    h-index

  3. DD
    Daniel D. Gajski

    University of California, Irvine, United States

    8 publications · 158 citations

    8

    h-index

  4. GS
    Gurindar S. Sohi

    University of Wisconsin–Madison, United States

    8 publications · 611 citations

    8

    h-index

  5. ZZ
    Zhiru Zhang

    Cornell University, United States

    6 publications · 202 citations

    6

    h-index

1–5 of 1.2K

Institutions

360

  1. Intel (United States)

    Santa Clara, United States

    18 h-index

    37 publications

    1.8K citations

  2. University of Southern California

    Los Angeles, United States

    18 h-index

    46 publications

    2.3K citations

  3. University of Wisconsin–Madison

    Madison, United States

    13 h-index

    24 publications

    1.5K citations

  4. University of Minnesota

    Minneapolis, United States

    13 h-index

    17 publications

    639 citations

  5. University of California, Irvine

    Irvine, United States

    12 h-index

    27 publications

    1K citations

  6. Stanford University

    Stanford, United States

    11 h-index

    35 publications

    3.4K citations

  7. University of California, Los Angeles

    Los Angeles, United States

    11 h-index

    39 publications

    1.4K citations

  8. University of Michigan

    Ann Arbor, United States

    10 h-index

    28 publications

    2.2K citations

1–8 of 360

Venues

  1. IEEE Transactions on Computers

    18 publications · 951 citations

    16

    h-index

  2. 15

    h-index

  3. ACM SIGARCH Computer Architecture News

    18 publications · 1.6K citations

    14

    h-index

  4. 11

    h-index

  5. IEEE Journal of Solid-State Circuits

    9 publications · 291 citations

    9

    h-index

1–5