IEEE Transactions on Nuclear Science · 2005 · 123 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ModelingDevice SimulationIntegrated Circuit DesignPhysical DesignVery-large-scale Integration LayoutCharge CollectionFlip-flop ArchitectureFlip-flop DesignGuard PlacementHeavy Ion RadiationThree-dimensional Integrated Circuit Layout
A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.
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