IEEE Transactions on Electron Devices · 2007 · 34 citations · 13 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsMicrowave EngineeringCmos Circuit DesignDevice CharacterizationIntegrated Circuit DesignMicrowave Integrated CircuitsMicrowave MeasurementsMicrowave Network AnalysisLayout Parasitics ModelingMicrowave ModelingOn-wafer MeasurementOn-wafer Measurement TechniquesParasitic ExtractionRf Cmos DesignS-parameter CharacterizationStandards
This paper presents a general 4-port algorithm that can remove on-wafer parasitics from on-wafer measurements after impedance standard substrate (ISS) calibration of system errors, or remove both system errors and on-wafer parasitics in a single step without ISS calibration. On-wafer standards are fabricated on a 0.13 RF CMOS process, and experimental data are measured from 2 to 110 GHz using an HP 8510XF system. The impact of nonideal on-wafer load standards is examined using the deembedded transistor-parameters and the extracted small signal parameters. The errors remaining after the traditional open-short deembedding are numerically evaluated, which become significant above 50 GHz. The solved 4-port network for on-wafer parasitics is indeed reciprocal despite the assumptions of ideal OPEN and SHORT, thus allowing a mathematically simpler reciprocal 4-port solution. The general 4-port solution can also be directly applied to the measured raw S-parameters to remove both system errors and on-wafer parasitics in a single step. Single-step calibration leads to reasonably accurate transistor -parameters, despite the less accurate on-wafer standards compared to precision ISS standards.
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E.P. Vandamme, Dominique Schreurs, G. Van Dinther · IEEE Transactions on Electron Devices · 2001 · 256 citations
An effective gate resistance model for CMOS RF and noise modeling
Xiaodong Jin, Jia-Jiunn Ou, Chih‐Hung Chen et al. · 2002 · 166 citations