Parasitic Extraction
Parasitic Extraction is a computational methodology in integrated circuit design that identifies and quantifies unintended electrical elements—such as resistance, capacitance, and inductance—arising from physical layout structures, thereby enabling accurate post-layout simulation and verification of mixed-signal and analog circuits.
429
Publications
15.1K
Citations
1.3K
Authors
339
Institutions
Publications per year
2017–2026
47
429
1–5 of 429
1.3K
13
h-index
9
h-index
8
h-index
6
h-index
6
h-index
1–5 of 1.3K
339
Tsinghua University
Beijing, China
16 h-index
67 publications
1.7K citations
IBM (United States)
Armonk, United States
15 h-index
52 publications
1.4K citations
Carnegie Mellon University
Pittsburgh, United States
15 h-index
33 publications
851 citations
Massachusetts Institute of Technology
Cambridge, United States
14 h-index
35 publications
2.8K citations
University of Washington
Seattle, United States
10 h-index
22 publications
637 citations
Motorola (United States)
Schaumburg, United States
9 h-index
40 publications
1.5K citations
Texas Instruments (United States)
Dallas, United States
9 h-index
34 publications
727 citations
Intel (United States)
Santa Clara, United States
9 h-index
17 publications
766 citations
1–8 of 339
33 publications · 1.3K citations
24
h-index
25 publications · 1.9K citations
18
h-index
25 publications · 1K citations
17
h-index
13 publications · 325 citations
12
h-index
7 publications · 138 citations
7
h-index
1–5