Parasitic Extraction

Parasitic Extraction is a computational methodology in integrated circuit design that identifies and quantifies unintended electrical elements—such as resistance, capacitance, and inductance—arising from physical layout structures, thereby enabling accurate post-layout simulation and verification of mixed-signal and analog circuits.

429

Publications

15.1K

Citations

1.3K

Authors

339

Institutions

Publications per year

2017–2026

47

Authors

1.3K

  1. WY
    Wenjian Yu

    Tsinghua University, China

    17 publications · 355 citations

    13

    h-index

  2. NV
    N.P. van der Meijs

    Delft University of Technology, Netherlands

    9 publications · 347 citations

    9

    h-index

  3. JW
    Jacob White

    Massachusetts Institute of Technology, United States

    8 publications · 1.2K citations

    8

    h-index

  4. LD
    Luca Daniel

    Massachusetts Institute of Technology, United States

    6 publications · 153 citations

    6

    h-index

  5. YI
    Yehea Ismail

    Northwestern University, United States

    6 publications · 156 citations

    6

    h-index

1–5 of 1.3K

Venues

  1. 24

    h-index

  2. 18

    h-index

  3. IEEE Transactions on Electron Devices

    25 publications · 1K citations

    17

    h-index

  4. IEEE Electron Device Letters

    13 publications · 325 citations

    12

    h-index

  5. IEEE Microwave and Wireless Components Letters

    7 publications · 138 citations

    7

    h-index

1–5