SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration

Abstract

Scan testing has been proven to leak secret information through side-channel attacks. To ensure high security when testing crypto chips without compromising testability, a new secure scan architecture with key authorized test controlling is proposed. In this method, multiple test keys are uniquely integrated into the test vectors by employing a special key fill technique without increasing the test overhead in terms of test time and test data volume. The scan test process is properly initiated and operated relying on multiple levels of security authorization. With the key authorized test controlling scheme, the scan chains may be blocked against shifting out secure information to unauthorized users. The experimental results demonstrate the robustness of the proposed secure scan architecture while achieving the lowest test and hardware overhead compared to the existing approaches.