Ultra-high bandwidth memory with 3D-stacked emerging memory cells

Abstract

To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16bit 3D-stacked TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65nm CMOS technology indicates that the 3D-stacked memory has potential to achieve ultra-high bandwidth required for the future processors.