Impact of layout at advanced technology nodes on the performance and variation of digital and analog figures of merit

Abstract

New technologies and integration schemes introduced over the last few generations have increased the sensitivity of transistor performance and variation to its layout and environment. This paper describes an infrastructure for efficient statistical characterization of the transistor variation. The impact of the increased sensitivity of transistor characteristics to its layout and environment is illustrated through a variety of figures of merit for digital, analog and RF design. Examples of layout parameters and their interaction that cause a large variation in these figures of merit illustrate the applications of this infrastructure.