Scaling to Sub-1 nm Equivalent Oxide Thickness with Hafnium Oxide Deposited by Atomic Layer Deposition

Abstract

The implementation of gate dielectrics in sub- devices requires optimization of nanometer-thin layers, deposited, e.g., by atomic layer deposition (ALD). In this work, we optimize ALD conditions such as precursor pulse time and deposition temperature for layers with physical thicknesses below . Additionally, we investigate intermediate treatments in the ALD reaction cycle, such as exposure to gas-phase moisture or remote plasma at low temperature and thermal anneals. Such intermediate treatments affect both growth-per-cycle (GPC) and Cl-impurity content of the layers. The analysis of the process modifications allows a better understanding of the reaction mechanisms. pulse times of must be applied to achieve saturation in GPC and Cl content. Using saturated pulses decreases the gate leakage current in the sub- equivalent oxide thickness (EOT) range. The GPC is enhanced from for conventional ALD to for intermediate plasma treatments at low temperature. Intermediate anneals reduce the Cl content by about two orders of magnitude. Sufficient hydroxylation of the surface is one important factor controlling electrical properties in the sub- EOT range. The reduction of the Cl content does not systematically improve the electrical properties.