Japanese Journal of Applied Physics · 2008 · 10 citations · 6 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsMicrofabricationThin FilmsChip PackagingEtching ProcessesIntegrated Circuit DesignIntegrated Circuit FabricationMems FabricationMems PackagingCapacitanceCapacitorsMultichip ModulesSiliconSilicon EtchingThree-dimensional Integrated Circuit LayoutThree-dimensional IntegrationWet Etching
Embedded capacitors with available capacitances up to ∼80 nF have been implemented on a thin-film multichip module-deposited (MCM-D) substrate. By cost-effective silicon wet etching, a new metal–insulator–metal (MIM) structure named quasi-three-dimensional MIM capacitor has been realized. The groove structure formed by silicon wet etching increases effective capacitance area, thus enhancing capacitance density by 1.5 times. No additional mask or process step is required to form the groove structure since it is simultaneously patterned and etched with ground bumps that are for effective interconnection. The implemented capacitors have capacitances from 2 to 78 nF with a scalable density of 3.6 nF/mm2, indicating that they are excellent candidates for high-power decoupling application.
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Chip-package codesign of a low-power 5-GHz RF front end
S. Donnay, P. Pieters, Kristof Vaesen et al. · Proceedings of the IEEE · 2000 · 68 citations
Engineering, Computer Engineering, Electrical Engineering +17