The effect of gate recess profile on device performance of Ga/sub 0.51/In/sub 0.49/P/In/sub 0.2/Ga/sub 0.8/As doped-channel FET's

Abstract

The effect of gate recess profile on device performance of Ga/sub 0.51/In/sub 0.49/P/In/sub 0.2/Ga/sub 0.8/As doped-channel FETs was studied. In the experiment, Ga/sub 0.51/In/sub 0.49/P/In/sub 0.2/Ga/sub 0.8/As doped-channel FETs (DCFET's) using triple-recessed gate structure were compared with devices using single-recessed and double-recessed gate structures. It is found that triple-recessed gate approach provides higher breakdown voltage (35 V) than single-recessed (16 V) and double-recessed gate (28 V) approaches. This is attributed to the larger aspect ratio in the triple-recessed gate structure. A unified method to calculate the breakdown voltages of MESFETs, HEMTs and DCFETs (or MISFETs) of any given arbitrary recessed gate profile was proposed and used to explain the experimental results.