The effect of die attach voiding on the thermal resistance of chip level packages

Void-induced thermal impedance in power semiconductor modules: Some transient temperature effects

D.C. Katsis, J.D. van Wyk · IEEE Transactions on Industry Applications · 2003 · 152 citations

Engineering, Electrical Engineering, Materials Science +17

Measuring partial thermal resistances in a heat-flow path

M.R. Rencz, V. Székely · IEEE Transactions on Components and Packaging Technologies · 2002 · 124 citations

Engineering, Electrical Engineering, Materials Science +17

Thermal impact of solder voids in the electronic packaging of power devices

Ning Hua Zhu · 2003 · 61 citations

Engineering, Electrical Engineering, Materials Science +17

Modelling thermal effects of large contiguous voids in solder joints

L. Ciampolini, Mauro Ciappa, P. Malberti et al. · Microelectronics Journal · 1999 · 49 citations

Engineering, Electrical Engineering, Materials Engineering +17

Precision measurement and mapping of die-attach thermal resistance

Katsuo Kurabayashi, E. Goodson · IEEE Transactions on Components Packaging and Manufacturing Technology Part A · 1998 · 41 citations

Engineering, Materials Engineering, Materials Science +17