Enhanced Ge n⁺/p Junction Performance Using Cryogenic Phosphorus Implantation

Abstract

In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through fabricated n+/p junctions and n-type MOSFETs (nMOSFETs). In comparison with room temperature (RT) (25 °C) and hot (400 °C) implantation, cryogenic (-100 °C) implantation with a dose of 2.2e15 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> followed by a (400 °C) rapid thermal annealing leads to 1) lower junction leakage with higher activation energy and 2) lower sheet resistance with higher dopant activation and shallower junction depth. Gate-last Ge nMOSFETs fabricated using cryogenic implanted n+/p source/drain junction (2.2e15 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) exhibit lower OFF-current (upto 5x) and higher ON-current compared with RT (25 °C) and hot (400 °C) implanted nMOSFETs. This paper demonstrates that cryogenic implantation (-100 °C) can enable high-performance Ge nMOSFETs by alleviating the problems of lower activation and high diffusion of phosphorus in Ge.