Saurabh Lodha

Few-Layer MoS₂ <i>p</i>-Type Devices Enabled by Selective Doping Using Low Energy Phosphorus Implantation

Ankur Nipane, Debjani Karmakar, Naveen Kaushik et al. · ACS Nano · 2016 · 382 citations

Materials Science, Oxide Heterostructures, Electrical Engineering +14

Schottky barrier heights for Au and Pd contacts to MoS2

Naveen Kaushik, Ankur Nipane, Firdous Basheer et al. · Applied Physics Letters · 2014 · 280 citations

Materials Science, Semiconductors, Ii-vi Semiconductor +15

Near-Direct Bandgap WSe₂/ReS₂ Type-II pn Heterojunction for Enhanced Ultrafast Photodetection and High-Performance Photovoltaics

Abin Varghese, Dipankar Saha, Kartikey Thakar et al. · Nano Letters · 2020 · 237 citations · Full text

High performance 32nm logic technology featuring 2&lt;sup&gt;nd&lt;/sup&gt; generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong et al. · 2009 · 184 citations

Nm Logic Technology, Electrical Engineering, Engineering +13

A 32nm logic technology featuring 2&lt;sup&gt;nd&lt;/sup&gt;-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&amp;#x03BC;m&lt;sup&gt;2&lt;/sup&gt; SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost et al. · 2008 · 184 citations

Engineering, Vlsi Design, Channel Strain +17